Despite most discussion about chip manufacturing focusing on the leading edge and blazingly fast and complex side of the industry, the demand for the ‘legacy’ process technologies is also higher than ever, but also by volume a lot bigger than the latest and greatest. These legacy processes form the backbone of most modern electronics, and so being able to offer equivalent technology at lower cost/power is often a win-win for manufacturers and chip designers alike. To that end, Samsung is announcing a new 17nm process node, designed for customers still using a planar 28nm process, but want to take advantage of 14nm FinFET technology.

In modern processor design, a manufacturing process node comes with a set of design rules. To design a chip on that node, it has to follow those design rules. Usually those rules will have absolute worst-case limits, but if the chip designer can take advantage of the constraints to optimize their product, then it is of benefit to be intimately familiar with what can or cannot be done. As a result, a process like Samsung’s 28nm which uses planar transistors, will have a set of design rules different to that of Samsung’s 14nm, which uses 3D FinFET transistors. The design rules also take into consideration where to put the power, the connectivity, all the way up the metal stack from transistors to contact pads for packaging.

When it comes to manufacturing, at a high level there are two or three main segments to consider. The Front-End-Of-Line (FEOL) is where the manufacturing of the circuits starts, designing transistors. When we speak about leading edge technologies, it is the FEOL section that is inherently applied, because we need better and better tools to make smaller and smaller details in silicon to get the best transistors. Once the FEOL has done a number of layers with the transistors, the wafer moves to the Back-End-Of-Line (BEOL) for the rest of the circuitry – the BEOL takes care of putting in layers of connecting wires, power, and all the ancillary connections. After BEOL, the chips go to test, cutting up (dicing), and then packaging.

Sometimes the term Middle-of-Line or Middle-End-of-Line (MEOL) is used for chips with through-silicon-vias (TSVs) designed for multi-chip stacking.

At a holistic level, the FEOL and BEOL of any process node, say 28nm, has a 28nm version of design rules for both of those segments. Sometimes manufacturers will combine one set of design rules on FEOL with another on BEOL to produce a new product line, with some of the features of both. This is what Samsung is doing with its new 17nm / 17LPV (Low Power Value) process, announced today as part of Samsung's Foundry Forum event.

17LPV will combine the 14nm FEOL, so effectively the 14nm FinFET transistors, with a 28nm BEOL for connectivity. This means that customers can get the performance/power advantages of FinFET designs at an additional cost, without the extra cost of a denser BEOL. Ultimately the die size is likely still determined by the larger node BEOL, but the lower power transistors appear to be in demand. Samsung is claiming that 17LPV will over a 43% decrease in die area, 39% higher performance, or a 49% increase in power efficiency over a traditional 28nm process.

The first application for 17LPV will be in camera image signal processors, as part of Samsung’s CMOS Image Sensor portfolio. These chips aren’t necessarily requiring density, which makes 17LPV a good fit, but the optimized power and cost will benefit a specialised technology involved in stacking. Beyond that, Samsung is integrating 17LPV into its High Voltage offerings, targeting DDIC/Display Drivers that require high voltage support on the back-end combined with logic improvements.

Beyond 17LPV, Samsung Foundry is creating a 14LPU (we think this is still 28nm BEOL + 14nm FEOL) or Low Power Ultimate, for use with embedded MRAM and microcontrollers. 

The exact time scales of this new node have not been disclosed at this time, although Samsung Foundry’s representatives called the node part of a ‘paradigm shift’ inside the company when it comes to developing new specialty process solutions for these markets.

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  • Wereweeb - Wednesday, October 6, 2021 - link

    They also said they're bringing MRAM to the 14nm/17nm nodes, which could be very nice for ultra-low-power MCU's (Especially battery-powered and/or energy harvesting ones). Reply

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