AMD Zen Architecture Roadmap: Zen 5 in 2024 With All-New Microarchitectureby Ryan Smith on June 9, 2022 4:21 PM EST
Today is AMD’s Financial Analyst Day, the company’s semi-annual, analyst-focused gathering. While the primary purpose of the event is for AMD to reach out to investors, analysts, and others to demonstrate the performance of the company and why they should continue to invest in the company, FAD has also become AMD’s de-facto product roadmap event. After all, how can you wisely invest in AMD if you don’t know what’s coming next?
As a result, the half-day series of presentations is full of small nuggets of information about products and plans across the company. Everything here is high-level – don’t expect AMD to hand out the Zen 4 transistor floorplan – but it’s easily our best look at AMD’s product plans for the next couple of years.
Kicking off FAD 2022 with what’s always AMD’s most interesting update is the Zen architecture roadmap. The cornerstone of AMD’s recovery and resurgence into a competitive and capable player in the x86 processor space, the Zen architecture is the basis of everything from AMD’s smallest embedded CPUs to their largest enterprise chips. So what’s coming down the pipe over the next couple of years is a very big deal for AMD, and the industry as a whole.
Zen 4: Improving Performance and Perf-Per-Watt, Shipping Later This Year
Diving right in, AMD is currently in the process of ramping up their Zen 4 architecture-based products. This includes the Ryzen 7000 (Raphael) client CPUs, as well as their 4th generation EPYC (Genoa) server CPUs. Both of these are due to launch later this year.
We’ve seen bits and pieces of information on Zen 4 thus far, most recently with the Ryzen 7000 announcement at Computex. Zen 4 brings new CPU core chiplets as well as a new I/O die, adding support for features such as PCI-Express 5.0 and DDR5 memory. And on the performance front, AMD is aiming for significant performance-per-watt and clockspeed improvements over their current Zen 3-based products.
Meanwhile, AMD is following up that Computex announcement by clarifying a few things. In particular, the company is addressing questions around Instruction per Clock (IPC) expectations, stating that they expect Zen 4 to offer an 8-10% IPC uplift over Zen 3. The initial Computex announcement and demo seemed to imply that most of AMD’s performance gains were from clockspeed improvements, so AMD is working to respond to that without showing too much of their hand months out from the product launches.
Coupled with that, AMD is also disclosing that they’re expecting an overall single-threaded performance gain of greater than 15% – with an emphasis on “greater than.” ST performance is a mix of IPC and clockspeeds, so at this point AMD can’t get overly specific since they haven’t locked down final clockspeeds. But as we’ve seen with their Computex demos, for lightly threaded workloads, 5.5GHz (or more) is currently on the table for Zen 4.
Finally, AMD is also confirming that there are ISA extensions for AI and AVX-512 coming for Zen 4. At this point the company isn’t clarifying whether either (or both) of those extensions will be in all Zen 4 products or just a subset – AVX-512 is a bit of a space and power hog, for example – but at a minimum, it’s reasonable to expect these to show up in Zen 4 server parts. The addition of AI instructions will help AMD keep up with Intel and other competitors in the short run, as CPU AI performance has already become a battleground for chipmakers. Though just what this does for AMD’s competitiveness there will depend in large part on just what instructions (and data types) get added.
AMD will be producing three flavors of Zen 4 products. This includes the vanilla Zen 4 core, as well as the previously-announced Zen 4c core – a compact core that is for high density servers and will be going into the 128 core EPYC Bergamo processor. AMD is also confirming for the first time that there will be V-Cache equipped Zen 4 parts as well – which although new information, does not come as a surprise given the success of AMD’s V-Cache consumer and server parts.
Interestingly, AMD is planning on using both 5nm and 4nm processes for the Zen 4 family. We already know that Ryzen 7000 and Genoa are slated to use one of TSMC’s 5nm processes, and that Zen 4c chiplets are set to be built on the HPC version of N5. So it’s not immediately clear where 4nm fits into AMD’s roadmap, though we can’t rule out that AMD is playing a bit fast and loose with terminology here, since TSMC’s 4nm processes are an offshoot of 5nm (rather than a wholly new node) and are typically classified as 5nm variants to start with.
At this point, AMD is expecting to see a >25% increase in performance-per-watt with Zen 4 over Zen 3 (based on desktop 16C chips running CineBench). Meanwhile the overall performance improvement stands at >35%, no doubt taking advantage of both the greater performance of the architecture per-thread, and AMD’s previously disclosed higher TDPs (which are especially handy for uncorking more performance in MT workloads). And yes, these are terrible graphs.
Zen 5 Architecture: All-New Microarchitecture for 2024
Meanwhile, carrying AMD’s Zen architecture roadmap into 2024 is the Zen 5 architecture, which is being announced today. Given that AMD isn’t yet shipping Zen 4, their details on Zen 5 are understandably at a very high level. None the less, they also indicate that AMD won’t be resting on their laurels, and have some aggressive updates planned.
The big news here is that AMD is terming the Zen 5 architecture as an “All-new microarchitecture”. Which is to say, it’s not merely going to be an incremental improvement over Zen 4.
In practice, no major vendor designs a CPU architecture completely from scratch – there’s always going to be something good enough for reuse – but the message from AMD is clear: they’re going to be doing some significant reworking of their core CPU architecture in order to further improve their performance as well as energy efficiency.
As for what AMD will disclose for right now, Zen 5 will be re-pipelining the front end and once again increasing their issue width. The devil is in the details here, but coming from Zen 3 and its 4 instruction/cycle decode rate, it’s easy to see why AMD would want to focus on that next – especially when on the backend, the integer units already have a 10-wide issue width.
Meanwhile, on top of Zen 4’s new AI instructions, Zen 5 is integrating further AI and machine learning optimizations. AMD isn’t saying much else here, but they have a significant library of tools to pick from, covering everything from AI-focused instructions to adding support for even more data types.
AMD expects the Zen 5 chip stack to be similar to Zen 4 – which is to say that they’re going to have the same trio of designs: a vanilla Zen 5 core, a compact core (Zen 5c), and a V-Cache enabled core. For AMD’s customers this kind of continuity is very important, as it gives customers a guarantee that AMD’s more bespoke configurations (Zen 4c & V-Cache) will have successors in the 2024+ timeframe. From a technical perspective none of this is too surprising, but from a business standpoint, customers want to make sure they aren’t adopting dead-end hardware.
Finally, AMD has an interesting manufacturing mix planned for Zen 5. Zen 5 CPU cores will be fabbed on a mix of 4nm and 3nm processes, which unlike the 5nm/4nm mix for Zen 4, TSMC’s 4nm and 3nm nodes are very different. 4nm is an optimized version of 5nm, whereas 3nm is a whole new node. So if AMD’s manufacturing plans move ahead as currently laid out, Zen 5 will be straddling a major node jump. That said, it’s not unreasonable to suspect that AMD is hedging their bets here and leaving 4nm on the table in case 3nm isn’t as far along as they’d like.
Wrapping things up, the Zen 5 architecture is slated for 2024. AMD isn’t giving any further information on when in the year that might be, though looking at Zen 3 and Zen 4, both of those were/will be released later on in 2020 and 2022 respectively. So H2/EOY 2024 is as good as guess as any.
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mode_13h - Saturday, June 11, 2022 - linkIf AMD restricts it anywhere, I think it might be leaving it out of their APUs. But that would probably be about reducing die area, in which case the actual silicon wouldn't have it.
Khanan - Sunday, June 12, 2022 - linkThat makes more sense, yes. But I wouldn’t do it, it’s a leg up against Intel and a funny way to mock them.
mode_13h - Saturday, June 11, 2022 - link> Maybe they'll implement AVX-512 based on the pipes of two AVX-256 units.
One thing that makes AVX-512 annoying is the bigger vector registers. Also, there are twice as many of them. So, even if you duplex AVX2 instructions down half as many AVX-512 pipes, it still doesn't negate the die area impact.
Plus, AVX-512 adds different types of instructions than AVX/AVX2, which means additional dedicated logic with no other purpose.
Fulljack - Friday, June 10, 2022 - linkI don't know how relevant AVX-512 on server or workstation space, but I certainly doubt it will be relevant in consumer space.
still, I understand where AMD is coming from, though, as apparently they designed those chiplet to be used from Ryzen, Threadripper, and Epyc.
Khanan - Friday, June 10, 2022 - linkIt’s no problem since it’s 2x256 fused together instead of one big 512 bit unit.
mode_13h - Saturday, June 11, 2022 - linkIt's not that simple. There are operations with AVX-512 that don't map cleanly on to AVX2. In some cases, it's due to structural changes in the instruction set. In others, it's new element data types. And there are things like scatter/gather that AVX2 simply doesn't have.
BTW, AVX-512 even added support for the new instructions at narrower width. So, you can use them on 256-bit vectors without the full thermal impact of 512-bit processing.
Khanan - Sunday, June 12, 2022 - linkHowever, I don’t agree with the statement that if won’t be relevant in consumer space. Consumers can work with their PCs too, and the way normal desktop unfolded in the last years, more or less because of AMD, particularly the 16 core CPUs are for workstation not really for gaming, the least thing they are for is content creation. Intel is just a joke with their terrible efficiency, with Intel everything is just a complete joke, they make their top CPU a power hog which is unprofessional, it gives off a “gamey” vibe.
mode_13h - Saturday, June 11, 2022 - linkIt's pretty hard to make the case for AVX-512, outside of deep learning and HPC apps, I think.
There are some AVX-512 optimized string processing libraries and it's useful in video compression. However, GPUs are better for video compression, when they support it (and you don't need the absolute best quality).
shabby - Friday, June 10, 2022 - linkNo one's asking the real questions here... will we see a review of it on AnandTech?
Khanan - Friday, June 10, 2022 - linkI wouldn’t bet on it