TSMC: 3nm EUV Development Progress Going Well, Early Customers Engagedby Anton Shilov on July 23, 2019 3:00 PM EST
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Development of new fabrication technologies never stops at leading-edge companies such as TSMC. Therefore, it is not surprising to hear the annoucement that development of TSMC’s 3nm node is well underway, something the company publicly confirmed last week. As it appears, the manufacturing technology is out of its pathfinding mode and TSMC has already started engaging with early customers.
“On N3, the technology development progress is going well, and we are already engaging with the early customers on the technology definition,” said C.C. Wei, CEO and co-chairman of TSMC, in a conference call with investors and financial analysts. “We expect our 3-nanometer technology to further extend our leadership position well into the future.”
Since its N3 technology is in its early stages of development, TSMC doesn't currently talk about the specific characteristics of the process nor its advantages over N5. TSMC said that it had evaluated all possible transistor structure options for 3nm and came out with ‘a very good solution’ for its clients. The specification is under development and the company is confident it would meet requirements of its leading partnering customer.
One of TSMC’s arch-rivals, Samsung Foundry, plans to use nanosheet-based Gate-All-Around MBCFET transistors for its own 3nm (3GAAE) process technology. Since TSMC will have to be competitive with its rival, we expect the company to also advance its 3nm node significantly in comparison to its 5nm node. In fact, TSMC confirms that N3 is a brand-new process technology, not an improvement or iteration of N5.
Meanwhile, it is safe to say that that TSMC’s 3 nm node will use both deep ultraviolet (DUV) and extreme ultraviolet (EUV) lithography equipment. Since TSMC’s N5 uses up to 14 EUV layers, it is likely that N3 will go even higher in the amount of layers employed. The world’s largest contract maker of semiconductors also seems to be quite happy with its EUV progress and considers the technology important for its future.
- Samsung Announces 3nm GAA MBCFET PDK, Version 0.1
- TSMC’s 5nm EUV Making Progress: PDK, DRM, EDA Tools, 3rd Party IP Ready
- TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019
- TSMC Details 5 nm Process Tech: Aggressive Scaling, But Thin Power and Performance Gains
- TSMC Starts to Build Fab 18: 5 nm, Volume Production in Early 2020
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webdoctors - Tuesday, July 23, 2019 - linkThis is crazy news. Just as an FYI:
A hydrogen atom, for example, is about 0.1 nanometers, and a caesium atom is around 0.3nm. The atoms used in silicon chip fabrication are around 0.2nm. So you're going to have gates made up of about <50 atoms soon. That's amazing.
A5 - Tuesday, July 23, 2019 - linkIIRC, the "marketing node" has been decoupled from the actual smallest feature size for several years now. Still impressive, though.
Sivar - Tuesday, July 23, 2019 - linkMarketing atoms appear tiny at first glance, but show themselves to be much larger on average upon analysis of any depth.
DanNeely - Tuesday, July 23, 2019 - linkYou got that wrong. When examined in depth marketing atoms are found to be far smaller than they initially appeared; however they have huge spin values.
0razor1 - Wednesday, July 24, 2019 - linkOh, I signed in after ages to tip my hat to you, sir.
SSTANIC - Wednesday, July 24, 2019 - linkPoetry in a standing wave :)
PixyMisa - Wednesday, July 24, 2019 - linkPlus plus.
spkay31 - Wednesday, July 24, 2019 - linkYou get the "Walter Brattain and John Bardeen" award for humor in solid state physics! (Also know as the Schockley was an a-hole award.)
gfkBill - Friday, July 26, 2019 - linkWhere do I up-vote? Nailed it.
Dragonstongue - Tuesday, July 23, 2019 - linkLMFAO
I am pretty sure all lawyers, analyst and most politicians (most anyone when you go beyond making X per annum) causes that switch to flip :D