CoWoS
Currently the majority of high-end processors are monolithic, but design methodologies are slowly but surely shifting to multi-chiplet modules as leading-edge fabrication technologies get more expensive to use. In the coming years multi-chiplet system-in-packages (SiPs) are expected to become much more widespread, and advanced 2.5D and 3D chip packaging technologies will gain importance. To accelerate and simplify development of 3D designs, TSMC this week established its 3DFabric Alliance. While multi-chiplet SiPs promise to simplify development and verification of highly complex designs, they require brand-new development methodologies as 3D packages bring a number of new challenges. This includes new design flows required for 3D integration, new methods of power delivery, new packaging technologies, and new testing techniques. To make the best use of the benefits of...
As HPC Chip Sizes Grow, So Does the Need For 1kW+ Chip Cooling
One trend in the high performance computing (HPC) space that is becoming increasingly clear is that power consumption per chip and per rack unit is not going to stop...
40 by Anton Shilov on 6/27/2022
TSMC Q1 2021 Process Node Revenue: More 7nm, No More 20nm
This week TSMC has disclosed its full quarterly financial results for Q1 2021. In those results the company often explains where the revenue demand is for its technologies, and...
40 by Dr. Ian Cutress on 4/15/2021
3DFabric: The Home for TSMC’s 2.5D and 3D Stacking Roadmap
Interposers. EMIB. Foveros. Die-to-die stacking. ODI. AIB.TSVs. All these words and acronyms have one overriding feature – they are all involved in how two bits of silicon physically connect...
9 by Dr. Ian Cutress on 9/2/2020
2023 Interposers: TSMC Hints at 3400mm2 + 12x HBM in one Package
High-performance computing chip designs have been pushing the ultra-high-end packaging technologies to their limits in the recent years. A solution to the need for extreme bandwidth requirements in the...
35 by Andrei Frumusanu on 8/25/2020
TSMC’s Version of EMIB is ‘LSI’: Currently in Pre-Qualification
Whilst process node technologies and Moore’s Law are slowing down, manufacturers and chip designers are looking to new creative solutions to further enable device and performance scaling. Advanced packaging...
19 by Andrei Frumusanu on 8/25/2020
TSMC Teases 12-High 3D Stacked Silicon: SoIC Goes Extreme
I’ve maintained for a couple of years now that the future battleground when it comes to next-generation silicon is going to be in the interconnect – implicitly this relies...
15 by Dr. Ian Cutress on 8/25/2020
TSMC & Broadcom Develop 1,700 mm2 CoWoS Interposer: 2X Larger Than Reticles
With transistor shrinks slowing and demand for HPC gear growing, as of late there has been an increased interest in chip solutions larger than the reticle size of a...
18 by Anton Shilov on 3/4/2020
Arm & TSMC Showcase 7nm Chiplet, Eight A72 at 4GHz on CoWoS Interposer
Arm and TSMC this week unveiled their jointly developed proof-of-concept chip that combines two quad-core Cortex-72-based 7 nm chiplets on TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) interposer. The two chips are connected...
26 by Anton Shilov on 9/27/2019
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